As a method of implementing synchronization in a fault tolerant computer, there is a synchronization scheme called a lock step. In the lock step, when the same “initial state and execution command of central processing units (CPUs)” are given to calculators, states are matched with each other between two systems by executing the same command from the same initial state using determinativeness of the calculators in which calculation results are the same. An instruction lock step which is a kind of lock step is a scheme of matching states of cores and memory of CPUs in execution command units of the CPUs between two systems.
In the case of symmetric multiprocessing (SMP), information regarding an access order to a shared memory is used as calculation information as well as “an initial state and an execution command of a CPU” for the purpose that the results of calculations executed asynchronously between two systems are the same. Therefore, as the instruction lock step corresponding to the SMP, a scheme is adopted in which when synchronization is executed, two calculators are configured to have roles of a precedence system and a delay system, an access order and access content are recorded on a shared memory in the precedence system, the access order and the access content are transferred to the delay system, and the calculation is reproduced. That is, after a calculation result of the precedence system is confirmed, the calculation is then reproduced in the delay system. Therefore, until the calculation result of the precedence system is transferred, a delay time occurs in the delay system.
When the flow of the process is described in brief, calculation is started by the precedence system. Then, the precedence system transfers data of access to the shared memory generated during the calculation, data of a generated output request, and register values of cores as the calculation result to the delay system. Here, the calculation of the precedence system stops.
When the delay system receives the calculation result from the precedence system, the delay system reproduces the calculation. Then, the delay system compares the reproduction result of the calculation to the calculation result received from the precedence system and notifies the precedence system of the comparison result. The precedence system receives the comparison result from the delay system. In this case, when the comparison result indicates that the calculation results match each other, the precedence system executes output to an external device in response to an output request. Then, the calculation of the precedence system resumes.
However, in the related art, when a process is executed by the above-described flow without consideration of a case in which many cores are included in the CPU, the cores of the precedence system which have not executed the output also stop calculation until the reception of the comparison result from the delay system. For this reason, calculation resources may not be utilized effectively.
As a related technical document, there is Japanese Laid-open Patent Publication No. 2004-46599.